Indexed, peer‑reviewed, rapid editorial decisions

Journal of Electrical Engineering and Technology: computers in engineering at system scale

Reach a global audience at the frontier where engineering and computers converge: power systems, control, embedded and real‑time software, diagnostics, and AI‑enabled automation. Transparent review, fair APCs, and reproducible research practices help your work get adopted in labs and industry.

Submission fast‑lane

Submit to the journal of electrical engineering and technology focus track to accelerate visibility for hardware‑verified algorithms, control designs, and firmware with real‑world constraints. Provide clear benchmarks, operating envelopes, and fail‑safe modes for a smooth review.

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Engineering and computers Computers in engineering Embedded & control

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Peer‑reviewed

Transparent decisions, versioned feedback, and practical guidance for deployment in safety‑critical and real‑time environments.

Indexing & academic recognition

Scope aligned to the journal of electrical engineering and technology

We welcome rigorous work that integrates power, control, and computation. If your study shows measurable reliability, efficiency, or safety improvements—validated on hardware or high‑fidelity platforms—our audience of practitioners and scholars will find it immediately relevant.

Representative domains

Power & control systems — Grid integration, converters, storage, MPC, robust and adaptive control, and protection strategies under transients and harmonics.

Embedded & real‑time software — RTOS scheduling, mixed‑criticality, memory‑safe drivers, interrupts, DMA, and timing analysis with jitter/latency envelopes.

Signals, sensing, diagnostics — Condition monitoring, sensor fusion, fault detection/isolation, and drift‑aware calibration strategies, including ML with error bars.

Cyber‑physical security — Hardened firmware, authenticated control channels, anomaly detection at the edge, and recovery from degraded modes.

Fit for engineering and computers manuscripts

Submissions at this interface succeed when they show disciplined experimentation, defined operating boundaries, and the precise trade‑offs behind each design decision. The more you clarify assumptions and replicable test procedures, the faster your review.

Evidence that stands out

• Hardware‑in‑the‑loop or real‑plant validation
• Deterministic test scripts and reproducible seeds
• Clear baseline comparisons and ablation studies
• Versioned firmware/build flags with configs

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Prefer a quick start? Use our guided checklist, then upload directly. Your manuscript enters editorial triage within hours.

Tracks for computers in engineering contributions

Choose a track that matches your primary claim and the maturity of your artifacts. You may combine tracks when your work spans multiple layers (e.g., power electronics with firmware co‑design).

Track A: Hardware‑validated control and power

Ideal for converters, drives, microgrids, protection, and real‑time controllers. Detail switching behavior, EMI constraints, thermal headroom, and safety margins under worst‑case load.

Evidence Fault response curves, harmonic spectra, stability under rapid transients, and HIL/plant datasets with configs.

Artifacts Controller parameter ranges, tuning scripts, and deployment notes (rollback and monitoring hooks).

Track B: Embedded, firmware, and real‑time

Focus on determinism, jitter budgets, interrupt latencies, and failure isolation. Include memory footprints, task priorities, and timing diagrams aligned to claims.

Evidence Latency distributions, ISR timing, stress tests, watchdog triggers, and recovery from degraded modes.

Artifacts Build flags, RTOS configs, pin maps, logs, and a minimal harness for replication.

Track C: Signals, diagnostics, and AI

For condition monitoring, predictive maintenance, and resilient sensing pipelines. Emphasize data quality, realistic noise models, and calibration robustness.

Evidence ROC/PR curves with confidence intervals, ablations for sensor drift, and on‑edge compute benchmarks.

Artifacts Dataset cards, schema docs, and versioned preprocessing scripts.

Track D: Systems & security

Cyber‑physical security, authenticated control channels, redundancy, and defense‑in‑depth for critical infrastructure.

Evidence Threat models, latency/throughput under security controls, and fault injection results.

Artifacts Policy templates, key rotation procedures, and test harnesses for secure boot/updates.

Research Manuscript Submission Low Publication Fee Journals Fast Track Submission

journal of electrical engineering and technology indexing and visibility

Boost findability by naming components and control modes in captions and abstracts. Clear terms help your engineering and computers work surface in targeted searches.

How to prepare a high‑impact engineering and computers manuscript

Start with the bottleneck you removed—switching losses, PLC latency, firmware race conditions, sensor drift, or grid instability—and quantify the improvement. Explain constraints (thermal, EMI, safety) and how your design remains stable across those bounds. Then show rigorous baselines and transparent ablations.

Reviewer‑favored narrative

Motivation — Define the real user risk, reliability gap, or cost driver your method addresses.

Design — Clarify architecture, control‑compute partitioning, and interfaces across hardware/firmware/software.

Evaluation — Provide error bars, stress envelopes, and repeatable conditions that match claims.

Limits — Describe operating boundaries, failure modes, and safe fallbacks.

Adoption — Offer integration guidance and monitoring hooks for deployment.

Replication essentials

Make it easy for another lab to rebuild your results. Clear artifacts compress review time and increase citations.

ConfigsController gains, firmware versions, RTOS priorities, build flags, and PCB revisions.

DatasetsSchema, labeling strategy, sensor specs, and calibration notes.

ScriptsTest harness, seed files, and log parsers to regenerate tables and figures.

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Ethics, integrity, and reproducibility policy

Trustworthy research in computers in engineering demands transparency. Declare data provenance, safety protocols, and any constraints that influenced test setups. When in doubt, over‑document—reviewers reward clarity.

What to disclose

Safety safeguards — Interlocks, thermal cutbacks, and protective settings used during trials.

Environmental factors — Ambient temperature, supply ripple, and EMI conditions relevant to claims.

Standards & codes — Any compliance targets (EMC, functional safety, grid codes) that shaped your design.

Limitations — Known failure modes or operational regimes not covered by evidence.

Anti‑plagiarism and authorship

Submit only original work. Cite prior art, including datasets, frameworks, and baseline implementations. Align author contributions to tasks (design, experiments, analysis, writing) for transparency.

Tip: Include a concise artifact checklist and link it in your cover letter for a faster desk assessment.

Original Research Submission Open Access Submission Where we’re indexed

Author benefits: visibility, speed, and practical impact

We optimize for clarity and adoption. Your engineering and computers results are more than plots—they’re blueprints others can build on. We prioritize fair review cycles, detailed feedback, and strong discoverability.

Why authors choose this venue

Predictable timelines — Rapid triage, with clear expectations and responsive communication.

Real‑world emphasis — Credit for hardware validation, safety margins, and operating envelopes.

Findability — Guidance on keywords, captions, and component naming that match search behavior.

Open access options — Reach both academic and industry readers swiftly.

Optimize your discoverability

Use precise terms your peers search for. Place key component names and control modes in the abstract, figure captions, and section headings.

sensorless FOC inverter SVPWM droop control IEC 61850 CPS timing

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Practical blueprint for a compelling submission

Use the outline below to align your manuscript with reviewer expectations in computers in engineering contexts. This structure keeps technical depth while highlighting proof of reliability and safe operation.

Recommended sections

AbstractProblem, constraints, measurable gains, brief methods, and key results with numbers.

IntroductionGap analysis, contributions, and a concise threat or risk model where applicable.

System modelPlant, controller, and compute stack, including timing and safety assumptions.

MethodAlgorithms and control laws with complexity/timing considerations.

EvaluationBenchmarks, stress tests, and error bars; document ambient and power conditions.

LimitationsOperating boundaries, failure handling, and lessons learned.

DeploymentIntegration checklist, rollback plan, and monitoring hooks.

Common pitfalls to avoid

Under‑specifying conditions — Don’t omit thermal, EMI, or supply ripple contexts that change outcomes.

Unclear baselines — Use field‑trusted baselines; deviations need a rationale and ablations.

Opaque artifacts — Missing configs or seeds block replication and slow review.

Attach a short README in your supplementary material listing configs, datasets, and re‑run steps.

Manuscript Submission Publish Your Article Publish in International Journal of Computer Applications

FAQ for authors

How does the journal of electrical engineering and technology focus improve time‑to‑decision?

Clear fit criteria and a disciplined artifact checklist shorten desk evaluation. Hardware‑validated claims with transparent bounds typically move fastest.

Can I submit combined topics across engineering and computers, such as power electronics with embedded ML?

Yes. Choose a primary track and cross‑reference additional evidence where needed. Clarify resource budgets and explain safety fallbacks for ML‑in‑loop systems.

What improves acceptance odds for computers in engineering papers?

Credible baselines, error bars, repeatable seeds, and real‑world constraints improve trust. Share configs, logs, and a small test harness.

Do you support open access and fast publication?

Open access options are available. Fast‑track consideration is possible for well‑documented, safety‑aware submissions that demonstrate robust evidence.

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